CVE-2024-42279

In the Linux kernel, the following vulnerability has been resolved:

spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer

While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer.

This vulnerability is rated as Moderate severity because exploitation requires local access and specialized Microchip SPI controller hardware, limiting any potential data leakage or integrity issues to residual bus traffic. The flaw stems from stale data persisting in FIFO queues between successive serial peripheral interface transactions when a previous operation omitted receive handling. Supported Red Hat Enterprise Linux releases are not affected, as the affected driver was introduced in a newer upstream kernel release and is not present in standard enterprise kernels.

The CVSS score(s) listed for this vulnerability do not reflect the associated product's status, and are included for informational purposes to better understand the severity of this vulnerability.